FPGA Design Flow

The complete FPGA flow including the synthesis process of HDL code consists of a number of processes which are:-

source:https://allaboutfpga.com/fpga-design-flow/

1] Design

This is the first process in the FPGA design flow. From the specification, several factors need to be determined first such as complexity of the block, total number of I/O's, frequency of the block, and power consumption along with optimization.

There are several methods for design entry. It can be schematic-based with the help of GUI and then needs to be invoked using instance name and proper instance name. The design can also be entered using HDL based entry.

Depending on the complexity of the block, one can choose.


2] Logic Synthesis

The whole process of converting an RTL code either a Verilog/VHDL code into a gate-level the netlist can be broadly classified into the following three processes:-

  • Translate
  • Optimization
  • Gate level mapping
So let's start with each of the processes:-

The first process combines the process of converting RTL codes to an un-optimized Boolean logic and in this process, all the constructs of the Verilog/VHDL coding are converted into some form of description which is only done by the tool and not by the designer.

The next process is to convert the unoptimized Boolean logic into the optimized Boolean description and it can be done by the use of an algorithm where the unoptimized format is first converted into some PLA(Programmable Logic Array) format and it finally again optimized by using variables. But this optimization technique again can be divided into two parts which are flattening and factoring and they take the help of AND/OR logic to either break down a logic level or to combine them depending on the complexity of the block.

The last process is the gate-level mapping in which the optimized description is converted into a gate-level netlist with the help of the parameters taken from the technology library.

3] Implementation

This process is again subdivided into three major steps:-
  • Translate
  • Map
  • Place and Route
All the above three steps combined start the process of implementing a design to make it fit for programming.

The translation process consists of all the netlist file generated from the previous steps and all the information is saved in NGD (Native Generic Database) file. The timing constraint of the file is also saved here which is in the form of UCF(User Constraint File).

After that, a sanity functional simulation needs to start to check whether the design has been working asper intended. Some logical bugs if occurred need to be fixed in this process before proceeding to the next step.

The next process is a map that takes the NGD file as input and generates the NCD (Native Circuit Description) to fit the design in the FPGA block.

The next step is to place and Route in which the location of each cell needs to be specified in block and routing does the connection between the cells and the block.

4] Static Timing Analysis

In this process, the tool will check for any timing-related errors. Setup time, hold time, delay calculation, path related errors should be fixed in this step.

5] Device Programming

This is the step in which the design is to be entered in FPGA and the design file is loaded through.BIT file and the programming logic to be used is BITGEN.


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